Non-volatile memories called, for example, flash memories or the like have their individual data stored therein such as, for example, the name of their manufacturer, the model number of product, the manufacture number and the like, and then are shipped or forwarded as products. A timing of making an individual data store in each semiconductor device is often on the way of inspection for a semiconductor device after it is transferred from a manufacture line to an inspection line, and there are many cases that the individual data is written in each semiconductor device on the way of inspection.
FIG. 2 shows a rough construction of a prior art semiconductor device testing apparatus in which individual data of semiconductor devices can be written therein. Testing of a semiconductor device, particularly, a memory thereof is performed in such manner that a predetermined test pattern is stored in a memory under test, the test pattern stored in the memory is read out thereof, the read-out data and an expected value are compared, and when the read-out data disagrees with the expected value, a decision is rendered that a failure cell exists in a memory cell at the address where the disagreement therebetween occurs. Also, in case of testing a non-volatile memory, testing therefor is performed in a similar manner.
In the semiconductor device testing apparatus shown in FIG. 2, only a construction thereof that a test pattern is written in semiconductor devices DUT1-DUTn under test is shown. That is, a timing of the rise or leading edge and a timing of the fall or trailing edge of a test pattern signal to be applied to the semiconductor devices DUT1-DUTn under test are stored in a timing data generator 11, these timings being freely set in advance by a user, and the timing data are sent to a timing generation part 15. In the timing generation part 15 are generated a set pulse SP and a reset pulse RP each being set to be generated at a timing delayed by a predetermined delay time from the initial phase position of a test cycle in accordance with the timing data and a logical value of pattern data sent from a pattern data generator 12.
The set pulse SP and the reset pulse RP outputted from the timing generation part 15 are branched at branch points J1 and J2 in correspondence to the number of the semiconductor devices DUT1-DUTn under test. The branched set pulses and reset pulses are applied to waveform generation parts 18A-18N through variable delay elements 17 inserted in respective branched paths for phase matching, respectively.
Each of the waveform generation parts 18A-18N consists of a S-R flip-flop to the set terminal S of which is applied the set pulse SP thereby to control a timing of the leading edge of the test pattern signal. Also, the reset pulse RP is applied to the reset terminal R of the S-R flip-flop thereby to control a timing of the trailing edge of the test pattern signal. Further, a waveform control part 15A is a control part for controlling whether to generate test pattern signals having, for example, NRZ waveforms or RZ waveforms or other waveform modes from the waveform generation parts 18A-18N, respectively. The waveform modes are previously set in the waveform control part 15A prior to the start of testing.
The test pattern signals generated from the waveform generation parts 18A-18N are applied to corresponding pins of the semiconductor devices DUT1-DUTn under test through respective drivers 19A-19N, respectively. FIG. 2 shows the construction that the test pattern signals are applied to one of pins of the respective semiconductor devices DUT1-DUTn under test. Accordingly, in practice, the construction shown in FIG. 2 is provided by the same numbers as that of pins of each of the semiconductor devices DUT1-DUTn under test.
Here, there will be described an additional explanation as to the construction of the timing generation part 15. The timing generation part 15 comprises: the waveform control part 15A for generating a set signal SET and a reset signal RST on the basis of pattern data supplied from the pattern data generator 12 and a waveform mode previously set; an integer delay generation part 15B for generating a delay time corresponding to as much as an integer times a period of a reference clock REFCLK in timing data supplied from the timing data generator 11; a fraction delay data generation part 15C for generating a delay data corresponding to as much as a fraction shorter than a period of a reference clock REFCLK in timing data supplied from the timing data generator 11; and a pair of fraction delay generation parts 15D and 15E for giving a fraction delay time to a set pulse SP in accordance with a fraction delay data generated in the fraction delay data generation part 15C.
The fraction delay data generation part 15C applies a start signal and a fraction delay data to the fraction delay data generation part 15C at a timing that a delay time corresponding to an integer times a period of the reference clock REFCLK generated in the integer delay generation part 15B has passed, and the waveform control part 15A outputs a set signal SET in synchronism with the start signal. If the set signal SET should be a logical “1”, for example, that indicates the rise of a test pattern signal, the fraction delay data generation part 15C sends a fraction delay data that defines a timing of the rise to the fraction delay generation part 15D.
In addition, if a reset signal RST being outputted from the waveform control part 15A should be a logical “1” that indicates the fall of a test pattern signal, the fraction delay data generation part 15C sends a fraction delay data to the fraction delay generation part 15E on the side of the fall.
In such manner, a timing of the rise of and a timing of the fall of a test pattern signal are defined, and this test pattern signal is applied in common to pins of all of the semiconductor devices DUT1-DUTn under test.
Next, the operation of writing data individually in each of the semiconductor devices DUT1-DUTn under test will be described. Individual data to be written individually in each of the semiconductor devices DUT1-DUTn under test is stored in an individual data storage part 13. In case of writing individual data, a multiplexer 14 is changed over such that its contact is connected to its terminal B, and the individual data is inputted into the timing generation part 15 in place of pattern data.
The individual data to be applied to each of the semiconductor devices DUT1-DUTn under test is composed of a series of one bit data as to each input pin, and this series of one bit data is prepared by a plurality of series for a plurality of pins thereby to form a parallel data representing a letter, a character, a sign, a symbol or the like. Like the pattern data, a set pulse and a reset pulse are applied to each of the waveform generation parts 18A-18N in accordance with a combination of logical “1” and logical “0” of the parallel data. In each of the waveform generation parts 18A-18N, a waveform of logical “1” or logical “0” is generated, and a code representing a letter or character or a code representing a sign or symbol is applied to each of pins of the semiconductor devices DUT1-DUTn under test so that data is written in each of the semiconductor devices DUT1-DUTn under test.
In case of writing data, in the prior art, a write-enable signal /WE is applied to one of the semiconductor devices DUT1-DUTn under test, and individual data (the name of maker, the name of device, serial number, and the like) corresponding to this one semiconductor device under test to which the write-enable signal /WE is applied, is written to the one semiconductor device under test. Such writing operation is carried out once for each of the semiconductor devices under test.
As discussed above, in the prior art semiconductor device testing apparatus, since a test pattern signal to be applied to the semiconductor devices DUT1-DUTn under test is distributed at the branch points J1 and J2, only the same test pattern signal can be applied to all of the semiconductor devices DUT1-DUTn under test on viewing at each moment.
In order to write respective individual data prepared in the individual data storage part 13 in the corresponding semiconductor devices DUT1-DUTn under test separately, it is necessary to apply a write-enable signal /WE separately to respective write-enable terminals of the semiconductor devices DUT1-DUTn under test, to read out the respective individual data prepared in the individual data storage part 13 one for each semiconductor device, and to write the read-out individual data in the semiconductor device under test selected by the write-enable signal /WE.
Consequently, it is required that the respective individual data must be written in the plural semiconductor devices DUT1-DUTn under test one individual data for one semiconductor device under test at a time. In case the respective individual data are written in the respective semiconductor devices DUT1-DUTn under test one individual data for one semiconductor device under test at a time, a time T required to write all of the individual data is as much as a write time t for one semiconductor device times the number N of the semiconductor devices, namely, T=t×N. Accordingly, the more the number N is increased, the more the time of writing the respective individual data is long. In the present status, there are many cases that N is equal to 64, namely, N=64.
As one method for removing such disadvantage, there is already known an invention disclosed in Japanese Patent Application Unexamined Publication No. 2002-083499 (JP, 2002-083499, A). The method disclosed in this Japanese Patent Application Unexamined Publication is characterized in that, as shown in FIG. 3, all of an individual data storage part 13; a multiplexer 14; and a timing generation part 15 comprising a waveform control part 15A, an integer delay generation part 15B and a fraction delay data generation part 15C is prepared by the number M of N times K (M=N×K) where N is the number of semiconductor devices DUT1-DUTn under test and K is the number of pins of each of the semiconductor devices DUT1-DUTn under test.
With the construction as stated above, when the individual data storage parts 13 are selected by switching the multiplexers 14 to connect their contacts with their terminals B, respective individual data can be applied to the corresponding semiconductor devices DUT1-DUTn under test from the individual data storage parts 13 at one time.
However, according to the construction shown in FIG. 3, the number M of the individual data storage part 13; the multiplexer 14; and the timing generation part 15 is equal to the product M of the number N of the semiconductor devices under test and the number K of pins of each of the semiconductor devices under test, namely, M=N×K, which results in a disadvantage that the scale of circuitry is much enlarged. By way of example, if N=64 and K=20, M comes to 1280. In addition, the power consumption is increased as the scale of circuitry is enlarged, and the generation of heat is also increased therewith. As a result, it is necessary to prepare a cooling means, which results in a disadvantage that the cost is higher.
It is an object of the present invention to provide a semiconductor device testing apparatus in which respective individual data can be written in corresponding semiconductor devices under test at one time with the avoidance of excessive enlargement in the scale of circuitry.